符合CCSDS标准的RS(255,223)译码器算法与FPGA实现

Algorithm and Implemention with FPGA of RS(255,223) Decoder According to CCSDS

介绍了符合CCSDS标准的RS(255,223)码的参数与译码器结构,给出了一种改进型无逆BM算法用于求解关键方程,使用Verilog语言完成了基于该算法的译码器设计与实现。测试结果表明,该译码系统性能优良,在尽可能节约硬件资源的同时满足了高速处理的需要。

The parameters and decoder structure of RS（255,223）according to CCSDS specification is introduced.It is given that the reformulated inversionless BM algorithm which is used to solve the key equation.The decoder based on this algorithm is designed and implemented with Verilog HDL.As test results shown,the decoder described in this paper decrease resource usage in a great deal at high speed.