AFMC:一种新的异步电路设计自动化流程

AFMC:A Novel Automated Flow for Asynchronous Circuit Design

随着VLSI面临的功耗及时钟问题越来越突出,异步电路及其设计方法得到了广泛关注.基于宏单元的异步电路设计流程能够采用现有的同步EDA工具和设计流程将同步电路转变成相应的异步电路.在基于宏单元的异步电路设计流程的基础上提出了一种新的异步电路设计自动化流程,并与解同步异步电路设计自动化流程进行了比较.在UMC 0.18μm工艺下采用提出的自动化流程设计实现了一款DLX异步微处理器,实验结果表明该流程能够快速地进行异步电路设计,并且在异步电路的数据通路性能优化方面具有一定的优势.相对于解同步DLX微处理器,采用基于宏单元的异步设计自动化流程实现的异步DLX微处理器能够获得6%左右的性能提高.

As the CMOS technology enters the deep submicron design era,the richness of computational resources brings a lot of problems,such as complex clock distribution,great clock skew and high power dissipation.Asynchronous circuit style is an efficient approach to solve the problems,and it is becoming significantly attractive to designers.The asynchronous circuit design flow based on macrocells can convert a synchronous circuit to an asynchronous counterpart efficiently using current EDA tools and industrial libraries for the synchronous circuit design.In this paper,a fully-automated asynchronous circuit design flow based on macrocells is presented,and it is also compared with the fully-automated desynchronization flow.The fully-automated desynchronization flow generates asynchronous circuits from the gate-level netlist,while our flow works from the register transfer level specification.Then,the proposed flow is used to implement a simple DLX RISC microprocessor in UMC 0.18 μm industrial library.The experiment shows that the fully-automated flow can accelerate the asynchronous circuit design and the logic delay of datapath in the macrocell based asynchronous circuit can be significantly optimized.Furthermore,the newly proposed flow can achieve an average of 6% speedups,when compared with the desynchronized DLX microprocessor for a subset of the Mibench benchmark suite.