低耗能流水线模数转换器的运算放大器设计与仿真

Design and Consideration of Low Power Operational Amplifier Implemented in Pipeline ADC

基于0.13,μm工艺,设计一个用于1.2,V低电压电源的10比特83MSPS流水线模数转换器的两级运算放大器.该放大器采用折叠共源共栅为第一级输入级结构,共源为第二级输出结构.详细介绍了运算放大器的设计思路、指标确定方法及调试中遇到的问题和解决方法.模拟结果显示:该运算放大器开环直流增益可达79.25,dB,在负载电容为2,pF时的单位增益频率达到838 MHz,在1.2,V低电压下输出摆幅满足设计要求,高达1 V,满足了10比特低电压高速度高精度模数转换器的要求.

Based on 0.13,μm technology a two-stage operational amplifier was designed which is used to 10-bit 83MSPS pipelined ADC of 1.2,V low-voltage power.The amplifier used a folded-cascode as first input stage,and common source as second output stage.The design procedure of the operational amplifier,parameter setting methods,simulation problems and solutions were introduced.Analogy simulation shows that,the open loop DC gain of the operational amplifier is 79.25,dB,and the unity gain frequency is 838,MHz when the load capacitance is 2 pF.In the low voltage of 1.2,V,output swing meets the design requirements,and up to 1V,it fulfills the requirement of ADC which is 10-bit low-voltage,high speed and high precision.