摘要
介绍了用于GEM（Gas Electron Multiplier）探测器读出的ASIC芯片GEMROC（GEM ReadoutChip）的设计。该芯片采用Chartered 0.35μm 2P4M CMOS工艺,单片集成16个读出通道,每个通道包括电荷灵敏前放（CSA）、CR-（RC）^2成形电路和驱动电路。增益和成形时间片外数字可调,适应于低噪声和高计数率应用。在默认增益4.6 mV/fC和成形时间160 ns情况下,仿真结果显示输出电压范围1.6～2.6V,非线性〈0.2%,噪声在探测器电容为20pF时仅～500e-。该设计已经版图实现并交付流片。
The design of the readout ASIC for GEM detector GEMROC is introduced.Using Chartered 0.35μm 2P4M CMOS process,GEMROC includes 16 readout channels in single chip,each channel consists of a charge -sensitive-amplifier（CSA）,a CR-（RC）^2 shaper and a buffer.The gain and the shaper time can be digitally programmed outside of the chip,allowing it to be used for low noise and high counting rate applications.In the default gain 4.6 mV/fC and shaper time 160 ns case,the simulation results show that the output voltage range is from 1.6～2.6 V,the nonlinearity is0.2%,the ENC is only about 500 e-when the capacitance of the detector is 20 pF.The design layout has been achieved and taped out for manufacture.
出处
《核电子学与探测技术》
CAS
CSCD
北大核心
2011年第3期289-292,311,共5页
Nuclear Electronics & Detection Technology
基金
中科院高能物理研究所创新项目资助
