期刊文献+

基于ADF4108的频率合成器设计

Design of Frequency Synthesizer Based on ADF4108
下载PDF
导出
摘要 本文分析锁相环(PLL)频率合成器的基本原理,并简单地介绍了ADI公司的集成锁相环芯片ADF4108的结构和性能。然后基于ADF4108芯片设计出一种频率合成器的方案,在该方案中,包含了环路滤波器的设计。通过ADIsimPLL3.1软件仿真,结果显示其相位噪声到达-99.27dBc@10kHz,并且系统工作稳定。 This paper analyses the basic principle of phase-locked loop (PLL)frequency synthesizer. And the internal structure and performance of the integrated PLL chip ADF4108 is described simply. Then, a scheme of PLL frequency synthesizer based on ADF4108 is given. In this scheme, the design of loop filter and VCO is included. The frequency synthesizer is simulated by the ADIsimPLL3.1 software, the simulation result shows that the phase noise of the frequency synthesizer can reach -99.27dBc@ 10 kHz and the system works stably.
出处 《自动化信息》 2011年第1期46-47,58,共3页 Automation Information
关键词 锁相环 环路滤波器 压控振荡器 相位噪声 Phase-locked Loop Loop Filter Voltage-controlled Oscillator Phase Noise
  • 引文网络
  • 相关文献

参考文献5

  • 1雷兆 王培章.基于ADF4107的锁相环仿真[J].测试测量技术,2010,(08).
  • 2马国胜,杨鹭怡.ADF4106及其在RF系统中的应用[J].世界电子元器件,2003(11):63-65. 被引量:6
  • 3远坂俊昭.锁相环(PLL)电路设计与应用.第3页.
  • 4Mehrotra,A. Noise analysis of phase-locked loops. Computer Aided De- sign, IEEE/ACM International Conference on 5-9,2000: 277-282.
  • 5Dean Banerjee.PLL Performance, Simulation, and Design. 2003.

共引文献5

;
使用帮助 返回顶部