基于FPGA图像分块解码的系统设计

FPGA-based Design of Image Block Decoding System

讨论了一种硬件实现卫星图像高速解码的系统设计方案。采用图像分块解码的方式,使用现场可编程门阵列(FPGA,Field Programmable Gate Array)的IP核实现片内缓存,减少了外挂RAM,降低了设计的复杂度。利用异步FIFO可以同时读写的特性,实现了码流检测与解码同时进行,并通过多路并行和流水线操作对图像码流进行高速解码。整个设计采用VHDL对算法完成建模和实现,仿真和综合结果表明该方案占用的硬件资源少,解码速度快,实现了图像码流解码的实时性和准确性,而且可移植性强,可以应用到图像处理的很多领域。

The hardware implementation of satellite image divided block decoding system design isdiscussed. A method for image divided block decoding is proposed,which uses the pipeline and multi-channel parallel operation to carry out high-speed decoding of the image stream and the IP Core of FPGA to achieve chip memory.So it can reduce the design complexity and external RAM.By the features of asynchronous FIFO it can read and write,and achieve detection and stream decoding simultaneously.The modeling and realization are implementation by VHDL. The experimental results show that this scheme,with less hardware resources,could realize fast decoding,and achieve real-time image-stream decoding and accuracy.And with its portability,it can be applied to many areas of image processing.