一种基于ME算法的RS译码器VLSI高速实现方法

A VLSI Design of High-Speed Reed-Solomon Decoder Based on the ME Algorithm

针对ME算法VLSI结构进行了分析,提出ME算法的流水线及最小化VLSI结构,以满足数据处理速率不断提高的需求。并利用该算法实现结构设计了一种低资源占用率、低成本的高速RS译码器。逻辑综合及仿真结果表明,基于A ltera公司Cyc loneII系列FPGA的RS(255,239)译码器,工作时钟达210 MHz,可满足数据速率1.68 Gb.s-1的编译码要求。

Based on an analysis of the ME algorithm＇s VLSI architecture,this paper proposes a Reed-Solomon decoder using pipelining and minimized architecture of modified Euclid algorithm to meet the demand of ever higher data rate in certain applications.The synthesis results show that this architecture can make RS（255,239） decoder operate at a higher clock frequency of 210 MHz in the Altera＇s Cyclone Family FPGA implementation and its data processing rate is 1.68 Gb·s-1.