期刊文献+

一种抗DPA攻击的双轨信号平行布线方法

A Dual-Rail Signal Parallel Routing Method to Counteract DPA Attacks
下载PDF
导出
摘要 双轨预充电逻辑是一种有效的差分功耗分析(DPA)攻击防护技术,其需要解决的关键问题在于必须保证互补的双轨信号线具有对称的电容负载。本文提出了一种双轨信号布线方法,能够基于商用的布局布线EDA工具实现双轨信号的平行布线,从而实现电容负载对称的目的。本方法首先利用EDA工具在奇数个布线轨道中对单轨网表进行布线,然后将信号线复制并平移到相邻的布线轨道得到双轨信号布线结果。这样,每对双轨信号线都有相同的布线结构,因而具有相同的电容负载。利用所提出的平行布线方法实现了一个AES加密协处理器,实验结果表明平行布线的双轨信号电容负载具有优异的对称性。 Dual-rail pre-charge logic is an effective technique to counteract differential power analysis(DPA) attacks.The key problem is to guarantee the symmetrical capacitive loads between true and false logics.A dual-rail signal parallel routing method based on commercial placerouting EDA is proposed in this paper to get symmetrical capacitive loads.Firstly,the single-rail nets are routed in odd routing tracks by EDA and then dual-rail wires are obtained by duplicating and moving the routed wires to the even routing tracks.As a result,each pair of dual-rail signal wires has the same routing structure and capacitance.The parallel routing method is implemented in an AES(Advanced Encryption Standard) coprocessor.The experimental results indicate that the capacitances of the dual-rail signal wires are perfectly balanced.
出处 《计算机工程与科学》 CSCD 北大核心 2011年第4期50-55,共6页 Computer Engineering & Science
基金 国家863计划资助项目(2009AA01Z124) 国家自然科学基金资助项目(60873016)
关键词 差分功耗分析攻击 双轨预充电逻辑 平行布线 differential power analysis dual-rail pre-charge logic parallel routing
  • 相关文献

参考文献12

  • 1Kocher P, JaffeJ, Jun B. Differential Power Analysis[C]// Proc of Int'l Cryptology Conf, 1999:388-397.
  • 2Ors S B, Gurkaynak F, Oswald E, et al. Power-Analysis At tack on an ASIC AES Implementation[C]//Proc of Int' Conf on Information Technology: Coding and Computing 2004:546-552.
  • 3Standaert F X, Ors S B, Preneel H. Power Analysis of an FPGA Implementation of Rijindael: Is Pipelining a DPA Countermeasure? [C]//Proc of Workshop on Cryptographic Hardware and Embedded Systems, 2004:30-44.
  • 4Oswald E, Mangard S. Herbst C, et al. Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers[C]//Proc of The RSA Conf Cryptographers Track, 2006: 192-207.
  • 5Tiri K, Akmal M, Verbauwhede I. A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards[C]//Proc of European Solid State Circuit Conf, 2002;403-406.
  • 6Tiri K, Hwang D, Hodjat A, et al. Prototype IC with WDDI. and Differential Routing DPA Resistance Assessment[C]//Proc of Workshop on Cryptographic Hardware and Embed ded Systems, 2005:354-365.
  • 7Mace F, Standaert F X, Hassoune I, et al. A Dynamic Cur rent Mode Logic to Counteract Power Analysis Attacks[C]// Proc of DCIS'04, 2004:186-191.
  • 8Popp T, Kirschbaum M, Zefferer T, et al. Evaluation of the Masked Logic Style MDPI. on a Prototype Chip[C]//Proc of Workshop on Cryptographic Hardware and Embedded Systems. 2007:81-94.
  • 9Yue D, Sun Y, Zhang M, ct al. A Look Up-Table Based Differential Logic to Coumeract DPA Attacks[C]//Proc of Int'l Conf on ASIC, 2009:855-858.
  • 10Tiri K, Verbauwhede I. Place and Route for Secure Stand ard Cell Design[C]//Proc of Int'l Conf on Smart Card Re search and Advanced Applications, 2004:113-158.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部