应用于GPS频率综合器的可编程分频器的设计

Design of a programmable frequency divider in GPS frequency synthesizers

设计了应用于全球定位系统（GPS）1．2GHz频率综合器中的可编程分频器。该分频器可实现600-700范围的分频比，并利用改进的均匀分频算法使分频输出波形的占空比更加理想。设计采用SMIC 0．18μm CMOS工艺标准单元的半定制设计方法，按照标准数字集成电路设计流程进行设计，包括Verilog代码编写、逻辑综合、版图规划、布局布线、后端时序仿真分析等过程。该可编程分频器模块已采用SMIC 0．18μm CMOS工艺进行流片，核心芯片面积为115μm×115μm。测试结果表明，通过控制芯片预置逻辑，分频器能与控制端口相匹配，完成分频功能，实现了预期结果。

A digital CMOS programmable frequency divider used in 1.2GHz frequency synthesizers for global position system （GPS） transceivers was designed. The frequency divider achieves a dividing ratio in the range of 600 to 700, and achieves a better duty cycle of the output wave form by using a proved even frequency dividing algorithm. The design was carried out according to the standard ASIC design flows, such as Verilog coding, logic synthesizing, layout planning, detailed routing, and post-layout simulation analyzing. The proposed structure, with its core chip area being 115μm×115μm was simulated and implemented using a standard SMIC 0.18μm CMOS logic process model and the experimental result shows that it can match the control port and work with a correct dividing ratio by the setting logic, so can accord- ingly achieve the expected result.