基于三种方法比较串行与流水线乘法器的功耗

The power dissipation comparison of serial and pipeline multiplierbased on three methods

乘法器是科学计算的重要硬件内核。为验证两种结构乘法器(串行、流水线)的功耗差异,分别采用三种功耗分析技术,包括QuartusⅡ自带功耗分析工具PowerPlay Power Analyzer Tool、Altera提供的FPGA估算实际功耗的经验公式,以及Synopsys的综合工具DC,结果表明,在可比较即计算位宽相同、所加工作频率相等的前提下,流水线乘法器的时延仅为串行乘法器的38.5%(因为前者强调了并行),消耗的硬件资源为后者的2.76倍。利用QuartusⅡ自带功耗分析功能得到的结果不明显,而经验公式估算法和DC工具法都得出串行与流水线乘法器功耗之比为0.36。

Multiplier is an important hardware core for scientific computing. To validate the power dissipation differences of two kinds of multipliers （ Serial, Pipeline ）, we took advantage of three kinds of skills to analyze their power consumption, including PowerPlay Power Analyzer Tool, the FPGA power consumption estimating formula applied by Altera, and the DC synthesis tool of Synopsys. Under our verification in condition of same calculating data width and working frequency, the results show that ） the delay of pipeline multiplier is 38.5% of serial multiplier for the reason of parallel; （ 2 ） the pipeline multiplier takes 1.76 times ALUs than serial one. Our power dissipation analysis conclusions show that （ 1 ） there is no clear difference by PowerPlay Power Analyzer Tool; （2） we grasped serial multiplier takes 36% of power consumption of pipeline one through both the estimating formula and DC synthesis tool.