基于FPGA的卷积码编译码器

Convolution encoder and decoder based on FPGA

基于卷积码的编译码原理,使用VHDL语言和FPGA芯片设计并实现了(2,1,3)卷积码编译码器。其中译码器设计采用"截尾"的Viterbi译码算法,在支路量度计算、路径量度和译码路径的更新与存储以及判决与输出等环节的实现中采取了若干有效措施,节省了存储空间,提高了设计性能。最后通过仿真验证了设计的正确性与合理性。

Based on the principle of convolution code, this paper presents the VHDL design of （2,1,3） convolution encoder and decoder which is designed by tail-biting viterbi decoding method. Some efficient measures is given in the process of representing branch metric, path metric, encoding branch updating and storage, decision and output. By using these measures, the hardware resources consumed are decreased, and the decoding speed is increased. Finally, the correctness and rationality of the design are verified by simulation.