一种AES-CCM 128 bit硬件加密器的优化设计

An optimized design of AES-CCM 128 bit hardware encryption device

介绍了一种基于FPGA的AES-CCM 128bit硬件加密器的优化设计方法。阐述了AES(高级加密标准)算法以及CCM工作模式,分析了AES算法的轮变换结构,并提出S-box查表结构和MixColumns(列混合运算)的VHDL语言程序设计思想。建立了ExpandedKey(密钥扩展运算)的数学模型,概括出AES算法的硬件实现方法,使得每一轮的轮变换与密钥扩展运算并行执行,以提高AES的加密速度。CCM工作模式结合了CTR与CBC-MAC工作模式,其加密明文或解密密文时都使用AES加密运算,这样解密过程就避免了繁杂的AES的直接解密运算。CCM模式下的简化加密协议,使用两个AES加密内核并行执行CTR与CBC-MAC工作模式以提高该模式下的加密解密速度。

The paper introduces an optimized design of AES-CCM 128 bit hardware encryption devices based on FPGA.It describes the AES（Advanced Encryption Standard） algorithm and the CCM mode.Analyze the round transformation structure of AES algorithm,and propose the VHDL program design of S-box look-up table structure and the MixColumns.Model the operation of ExpandedKey,summarizes the hardware implementation of AES algorithm,implement the round transformation and ExpandedKey operation in parallel,and then improve the speed of AES encryption.The CCM mode contains the CTR mode and the CBC-MAC mode,and the encryption and decryption of CCM mode uses the AES encryption algorithm,so the complex direct decryption is avoided.The simple encryption protocol of CCM mode implement the CTR and CBC-MAC mode use two AES encryption cores in parallel to improve the speed of encryption and decryption.