一种低开销双二元turbo译码器设计

Design of a Double Binary Turbo Decoder with Low Cost

设计一种低开销双二元turbo译码器,提出了一种能够适应滑动窗算法的交织器结构,通过与传统方案中的交织器联合使用,大大降低了交织与解交织过程所需要的存储单元.同时将取模归一化(modulo normalization)技术运用到双二元turbo译码器加比选(ACS)模块的设计上,缩短了关键路径的延时,提高了时钟频率和吞吐量.采用FPGA对译码器进行了验证,提出的译码器和传统的译码器相比,存储资源节省12%,和使用存储器存储交织/解交织地址的译码器相比,存储资源节省97%.

A low cost double binary turbo decoder was presented in this paper,with a new architecture of interleaver used.Through the combination with the interleaver used in traditional scheme,this interleaver which is applied to the sliding window algorithm can reduce memory bank needed for interleaving and deinterleaving.Modulo normalization was also used to design the add-compare-select（ACS） module of the double binary turbo decoder for high clock rate and throughput.The verification,based on FPGA,indicates the proposed decoder can reduce the memory size by 12%,comparing with the traditional one,and 97%,comparing with the decoder uses ram to store interleaving/deinterleaving address.