一种基于JTAG的CLB内建自测试方法

Build-In Self Test of CLBs Based on JTAG

针对Virtex-4型FPGA中可编程逻辑块故障检测的需求,提出了一种基于JTAG的内建自测试方法,并基于DEV++平台自行开发了基于并口的专用边界扫描测试软件.该方法可以比较可靠的检测FPGA中存在故障的可编程逻辑块,并能比较高的分辨率实现故障的定位.与传统的单故障检测方法相比,提出的改进型测试方法可以检测和定位多个故障CLB,并可以对故障类型进行诊断.实验结果表明:提出的测试方法可以精确的检测和定位存在故障的多个CLB,对具有类似结构的SRAM型FPGA具有普遍适用性.

This paper proposes a Built-In Self-Test approach able to detect and accurately diagnose all single and practically all multiple faulty configurable logic blocks（CLBs） in Virtex-4 FPGA with better diagnostic resolution.Unlike conventional BIST,the method proposed could detect and locate multiple fault CLBs concurrently.Based on the location of the fault CLBs,we could also identify their internal faulty modules or modes of operation.For the completion of fault testing,a testing program is developed.The testing result shows that the method proposed could accurately detect and locate the fault CLBs.This kind of method is easily scalable to other SRAM FPGA with similar architecture.