一种动态补偿、高稳定性的LDO设计

Design of a Dynamic Compensation and High Stability LDO

设计并实现了一种动态补偿、高稳定性的LDO。针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路。这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关。设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面积为400μm×650μm。设计的LDO工作电压为3.5～6.5 V,输出电压为3.3 V。结果表明,在提供100mA负载电流情况下电压差为200 mV,负载瞬态变化时最大输出电压过冲为100 mV,由电源电压变化和负载变化引起的输出电压误差分别为0.003%/V和0.005%/A,电源抑制比低频时为80 dB,1 kHz时为50 dB,整个电路的静态电流约为34μA。上述结果表明该LDO达到设计指标。

In this paper,a dynamic compensation,high accuracy LDO regulator is designed and implemented.At first,considering the characteristic that the loop stability changes with load current,a modified dynamic compensation circuit is proposed.The compensation circuit forms a dynamic zero which can track the LDO＇s output pole as the load current changes,so that the stability of the control loop is almost independent of load current.Based on CSMC 0.5 μm CMOS process,this work completes circuit design,physical layout,tape-out and chip test.The chip area is 400 μm×650 μm.The results show that the proposed LDO has the following characteristics： the operating voltage is 3.5～6.5 V,the output voltage is 3.3 V,the dropout voltage is 200 mV when it provides 100 mA load current,the maximum overshoot of output voltage is about 100 mV,the line regulation rate is 0.003%/V,the load regulation rate is 0.005%/A,the power supply ripple rejection is 80 dB at low-frequency and is 50 dB at 1 kHz,the total quiescent current is about 34 μA.These results show that the LDO basically meet the target of this design.