H.264中整数变换与量化的FPGA实现

A FPGA implementation of integer discrete consine transform and quantification for H.264 compression

H.264以其优异的压缩比率和高图像质量在实时网络视频通信、数字广播电视及高清视频存储播放等方面获得广泛应用。变换量化作为H.264编码框架中的一个基础模块,是熵编码前的一个重要处理过程,它的主要作用是使输入系数间数据相关性降低。鉴于之前大部分的变换量化是基于软件或协处理器来实现以及此种实现方式在速度及吞吐量上的局限,而硬件实现在速度和吞吐量上则具有很大的优势,因此研究H.264变换量化的硬件实现具有实用价值。采用高速并行处理的架构,基于寄存器传输级(RTL)用硬件描述语言完成了H.264中的整数离散余弦变换(IDCT)及量化算法的实现,并用Altera公司的CycloneⅡ系列可编程逻辑器件实现了硬件验证测试。设计方案消耗了10 489个逻辑单元,最高工作时钟频率为184.88 MHz,数据处理能力达到2 958 Mpixels/s,可在一个时钟周期之内完成对一个4×4矩阵数据的变换量化处理,可满足高速高吞吐量数据流处理的要求。

Due to its excellent compression rate and high image quality, H. 264 is widely applied in many regions, such as real-time internet video communication, digital television broadcast, HDTV and so on. As a key component of the H. 264 coding framework, integer discrete eonsine transform （IDCT） and quantification module takes on the rule of reducing the correlation coefficients of input data, which is an important pre-processing before the entropy coding. The normal realizations are based on software or hardware co-processor, in which way speed and throughput are limited. As a contrast, realization based on hardware can make up these shortages. In this paper, an FPGA implementation of integer discrete consine transform and quantification for H. 264 compression is introduced, which is based on a high throughput structure and is accomplished by register-transfer level （RTL） description. The whole design is tested on the Cyclone Ⅱ-based development board, DE Ⅱ. The resource cost is 10 489 LEs. Its maximal work frequency is 184.88 MHz, the maximal throughput is 2 958 Mpixels/s, and it can process a 4× 4 input data within a single clock period.