摘要
加法运算是数字系统中最基本的算术运算。为了能更好地利用加法器实现减法、乘法、除法、码制转换等运算,提出用Multisim虚拟仿真软件中的逻辑转换仪、字信号发生器、逻辑分析仪,对全加器进行功能仿真设计、转换、测试、分析,强化Multisim的使用,并通过用集成全加器74LS283实现两个一位8421码十进制数的减法运算,掌握了全加器的应用方法。测试证明,全加器功能的扩展和应用,利用Multisim软件的仿真设计能较好地实现。
Addition operation is the most basic digital system arithmetic. In order to achieve better use of adder subtraction, multiplication, division, transcoding operations, this paper proposed using Muhisim virtual simulation software, the logic of conversion device, digital signal generator, logic analyzer, the full adder design for functional simulation, conversion, testing,analysis,and strengthened the use of Muhisim and by using a full adder 74LS283 integrated to achieve a 8421 yards two decimal subtraction and master the application method of the full adder. Testing shows the expansion and application of full adder function can be well implemented by using simulation design of Multisim software.
出处
《电子设计工程》
2011年第9期111-114,共4页
Electronic Design Engineering
基金
学院校企合作资助项目(XTZY08G05)
