ETC中FM0解码器的设计

Design of FM0 decoder in ETC

FM0编码以其便于位同步提取、频谱带宽较窄、实现电路简单而在ETC中得到广泛的应用,线路FM0解码模块是ETC系统基带电路重要组成部分,本文基于ETC系统中车载单元(On board unit,OBU)与路边单元(Road sideunit,RSU)之间的短距离双向通信,以提高FM0解码速度的目的,根据FM0编码原则,在FPGA软件环境下用高级硬件描述语言VHDL实现FM0解码器设计,给出程序代码,在Quartus II环境下仿真,并通过逻辑分析仪观察波形。同等功能下,解码时间是图形输入法的五分之一。

Because of its ease of extraction,the narrow bandwidth of spectrum and the ease of achieving a simple circuit, the FM0 code has been widely used in the ETC. FM0 decoder is an important component of the baseband circuit in the ETC. In order to enhance the speed of FM0 decoding,the paper designs FM0 decoder by using VHDL based on the Short-range communication between OBU （On beard unit） and RSU （Road side unit） and the principle of FM0 encoding, gives the program code, compiles the results in Quartus Ⅱ software, and observes waveforms by the logic analyzer. Under the same function, the decoding time is one-fifth of that using graphical input method.