摘要
TLB(Translation Look-Aside Buffer,变换旁视缓冲器)是存储管理单元中完成访存地址转换的核心。但研究发现TLB工作时可以消耗微处理器芯片约17%的功耗。因此,TLB低功耗设计已经引起研究者的重视。通过对经典基准测试集程序访存行为的详细分析和仿真可知,在页面非连续访问时,页面间隔统计参数能够很好地指导TLB的低功耗设计。从这一角度出发,提出了低功耗的TLB设计方法。实验结果显示,改进后的TLB片上功耗明显降低。
Translation Look-Aside Buffer（TLB） is a dedicated hardware component that the Memory Management Unit（MMU） utilizes to improve page address tanslation speed.However,some researchers indicate that working TLBs may occupy as much as 17% of a processor＇s total power consumption.The objective of this paper is to effectively reduce the TLB on-chip power consumption by looking into the program behavior in respect of page access traits.With careful analysis of the memory access patterns of SPEC CPU benchmarks,we demonstrated that the Page Interval which non-sequential page accesses heavily exhibit can be used to largely reduce the power of TLBs.Based on this observation,we proposed a novel low-power TLB design methodology.Experimental results show that using our design the on-chip power consumption can be further saved.
出处
《计算机科学》
CSCD
北大核心
2011年第5期301-304,F0003,共5页
Computer Science
基金
国家自然科学基金重点项目(60736012)
国家自然基金项目(60773223)
国家"863"高技术研究发展计划基金项目(2009AA01Z110)资助
关键词
变换旁视缓冲器
低功耗
非连续访问
页面间隔
Translation look-aside buffer（TLB）
Low power
Non-sequential accesses
Page interval
