消除CMOS IC闭锁的外延加双保护环技术

The prevention of Latch-up in CMOS ICs by n^-/n+ Epi-layer and Double Guard Rings

本文简要描述了CMOS集成电路的闭锁机理,提出了消除CMOS集成电路闭锁的n^-/n^+外延加双保护环结构;把这种结构用于CC4066电路,在5.6×10~8Gy/s的γ瞬时剂量率下进行辐照实验,电路均不发生闭锁。最后得出,外延加双保护环结构,对中小规模电路而言,是一种消除CMOS电路闭锁的有效方法。

A structure of n-/n+ epi-layer combined with double guard rings to prevent CM OS ICs from latcn-up is presented in this paper, which has been used in CC4066. No latchup was observed in the circuit at a transient dose rate of 5.6×108Gy/s. It is concluded that the structure of epi-layer plus double guard rings is an effective way to prevent CMOS ICs from latchup for medium-and small-scale integrated circuits.