摘要
随着超大规模集成电路向高集成、高可靠性及低成本的方向发展,对集成电路制作过程中的全局平坦化提出了更高的要求.ULSI多层布线CMP中粗糙度对器件的性能有明显影响,因此本文主要研究多层互连钨插塞材料CMP过程中的表面粗糙度影响因素及控制技术,分析了抛光过程中影响粗糙度的主要因素,确定了获得较低表面粗糙度的抛光液配比及抛光工艺参数.
With the developing of ULSI to high density of integration,high reliability and low cost,the global planarization during IC fabrication are raised higher request.During CMP process,roughness of ULSI multilevel metallization layer influences the device performances directly.In this study,the key factors and controlling technology of influencing tungsten plug surface roughness during CMP process were studied,and the slurry optimal and polishing process parameters of gaining low surface roughness was gotten.
出处
《河北工业大学学报》
CAS
北大核心
2011年第2期1-5,共5页
Journal of Hebei University of Technology
基金
国家中长期科技发展规划02科技重大专项(2009ZX02308)
国家自然科学基金联合基金(NSAF10676008)
高等学校博士学科点专项科研基金(20050080007)
关键词
ULSI
多层布线
钨插塞
CMP
粗糙度
ULSI
multilevel metallization
tungsten plug
chemical mechanical polishing
roughness
