基于FPGA/Nios-Ⅱ的矩阵运算硬件加速器设计

Design and implementation of matrix hardware acceleration based on FPGA/Nios-Ⅱ

针对复杂算法中矩阵运算量大,计算复杂,耗时多,制约算法在线计算性能的问题,从硬件实现角度,研究基于FPGA/Nios-Ⅱ的矩阵运算硬件加速器设计,实现矩阵并行计算。首先根据矩阵运算的算法分析,设计了矩阵并行计算的硬件实现结构,并在Modelsim中进行功能模块的仿真,然后将功能模块集成一个自定制组件,并通过Avalon总线与NiosⅡ主处理器通信,作为硬件加速器。最后在FPGA芯片中构建SoPC系统,并在Altera DE3开发板中进行矩阵实时计算测试。测试结果验证了基于FPGA/Nios-Ⅱ矩阵运算硬件加速器的正确性、可行性以及较高的计算性能。

Due to the complex computation of matrix in many algorithms,the on-line computational performance of algo-rithm is low.To solve the problem,this paper proposes a novel scheme based on FPGA/Nios-Ⅱto implement the hardware accel-eration of matrix operation.According to the algorithm analysis,parallel computation structure of matrix operation is designed.After function verification in Modelsim,functional modules are integrated into a custom component.The custom component which is used as a coprocessor communicates with NiosⅡCPU by Avalon bus.To analyze the on-line computation performance of the hardware acceleration,an SoPC system is built up,then downloaded to the Altera DE3 board for the real-time test.The results show that the proposed scheme can improve the computational performance of matrix operation greatly.