WCDMA直放站数字下变频的FPGA实现

FPGA Implementation of Digital Down Converter in WCDMA Repeater

数字下变频器(Digital Down Converter,DDC)是WCDMA直放站的重要组成部分,它将高速采样的数字中频信号下变频到基带,然后进行抽取,低通滤波。重点研究了数字下变频器的数控振荡器NCO和半带滤波器的原理和硬件设计仿真,通过FPGA芯片Virtex-6 XC6VLX75T设计实现了适用于WCDMA直放站的数字下变频器,并对其进行硬件仿真与验证。

Digital down converter is an important part of WCDMA repeater.It lets the high-speed-sampled digital signals down-conversion to base band.Then extraction,low-pass filter are conducted.This paper focuses on the principle and hardware design of NCO part and HB decimation filter pat of digital down converter.Digital down converter,which is suitable for WCDMA repeater,is implemented in FPGA chip Virtex-6 XC6VLX75T.Finally,the hardware simulation and verification is completed.