基于CPLD的数字电子钟仿真研究

Based on CPLD Simulation Research of Digital Electric Clock

本文介绍了基于CPLD数字电子钟的设计方法,在CPLD内部规划了秒脉冲发生电路、两个60进制计数器(秒、分计数)、1个12进制计数器(时计数)。在MAX+PLUSⅡ软件中此电路得到了仿真验证。

This article describes the CPLD-based design method of digital electronic clock ,In the CPLD internal planning a second pulse circuit, two 60 binary counters （seconds, minutes count）, a 12-binary counter （time count）. In the MAX ＋ PLUS II software simulation of this circuit has been verified.