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可重构视频编解码处理器ReMAP设计 被引量：3

Design of Reconfigurable Processor ReMAP for Video Codec
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摘要 针对当前视频高清编解码的计算密集性、并行性和数据局部性的特点,提出一个粗粒度的可重构处理器ReMAP-2。该处理器由一个可重构的计算单元阵列构成,通过由临近直联和分段式总线组成的互联网络完成数据通信任务,具有良好的扩展性。计算阵列针对不同应用,通过加载不同配置信息流实时改变运算单元的计算功能和连接方式,支持多种格式的视频编解码应用。仿真验证表明,可重构处理器ReMAP-2在视频编解码应用时较常用的媒体处理器具有较大幅度的性能加速,处理性能达到或接近于ASIC水平,同时具有较高的应用灵活性。 A coarse-grain reconfigurable processor ReMAP-2 is proposed for video codec applications which shares several important characteristics： compute intensity,parallelism,and locality.ReMAP-2 comprises of a reconfigurable array of processing elements and interconnect network with neighborly connect and segment buses,which possesses good scalability.The architecture can change the function of processing elements and the data path of the reconfigurable array by uploading different configuration stream for different applications,which is suit for multiple standard of video codec.The simulation result shows that ReMAP-2 can achieve much better performance than common media processors.The compute capability is close to or same as ASIC implementation and meanwhile it has upstanding flexibility.
作者 戴鹏 雍珊珊 王新安 张兴
机构地区 北京大学深圳研究生院集成微系统科学工程与应用重点实验室
出处 《北京大学学报（自然科学版）》 EI CAS CSCD 北大核心 2011年第3期418-426,共9页 Acta Scientiarum Naturalium Universitatis Pekinensis
基金 863计划(2009AA01Z127)资助
关键词 可重构处理器 H.264 编解码 DCT 动态重构 reconfigurable processor H.264 codec DCT dynamic reconfiguration
分类号 TN919.81 [电子电信—通信与信息系统]
  • 相关文献

参考文献12

  • 1Joint Video Team. Draft ITU-T recommendation and final draft international standard of joint video specification. ITU-T Recommendation H.264 and ISO/IEC 14496-10 AVC, 2003.
  • 2khailany B, Dally W J, Kapasi U J, et al. Imagine media processing with streams. IEEE Micro, 2001, 21(2): 35-46.
  • 3Singh H, Lee M H, Lu G, et al. MorphoSys: an integrated reconfigruable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers, 2000, 49(5): 465-481.
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二级参考文献10

  • 1DeHon A. The density advantage of configurable computing. IEEE Transactions on Computers, 2000, 33 (4) : 41-49.
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  • 3Liu Yanliang, Dai Peng, Wang Xin'an, et al. Dynamic context management for coarse-grained reconfigurable array DSP architecture // ASICON2009. Changsha: IEEE Press, 2009:79-82.
  • 4Dai Peng, Wang Xin'an, Zhang Xing. Implementation of H. 264 algorithm on reconfigurable processor // PrimeAsia2009. Shanghai: IEEE Press, 2009:237-240.
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共引文献4

同被引文献30

  • 1Khailany B, Dally W J, Kapasi U J, et al. Imagine media processing with streams [J]. IEEE Micro, 2001, 21(2): 35-46.
  • 2Dai Peng, Wang Xin, an, Zhang Xing. Implementation of H. 264 algorithm on reconfigurable processorEC~// PrimeAsia 2009. Shanghai.. IEEE Press, 2009: 237- 240.
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  • 7Pham P, Mau P, Kim J, et al. An on-chip network fab- ric supporting coarse-grained processor array [ J]. IEEE transaction on Very Large Scale Integration (VLSI) Sys- tems, 2012, 21(1): 178-182.
  • 8Baumgarte V, Ehlers G, May F, et al. PACT XPP: a self-reconfigurable data processing architecture [ J]. The Journal of Supercomputing, 2003, 26(2): 167-184.
  • 9Singh H, Lee M H, Lu G, et al. MorphoSys: an inte- grated reconfigruable system for data-parallel and computa- tion-intensive applications [ J ]. IEEE Transactions on Computers, 2000, 49(5): 465-481.
  • 10Lattard D, Beigne E, Bernard C, et al. A telecom base- band circuit based on an asynchronous network-on-chip [ C]//IEEE International Solid-State Circuits Conference, Digest of Technical Papers. San Francisco (USA): IEEE Press, 2007: 258-601.

引证文献3

二级引证文献1

北京大学学报（自然科学版）
2011年 第3期

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