基于FPGA的时钟采样帧发生器设计

Design of Clock Sampling Frame Generator Based on FPGA

在串行通信中,为使系统具有灵活的可编程性和可移植性,减小系统体积,降低开发成本,详细地描述了一种时钟采样帧发生器总体结构。结合FPGA特性和VHDL语言,对时钟采样帧发生器各组成模块进行了接口定义,同时在ModelS im SE中进行了功能仿真验证。圆满完成了基于FPGA的时钟采样帧发生器IP核设计。通过实践表明,设计的时钟采样帧发生器IP核可靠易用,可扩展功能强,满足了实际应用系统的技术要求。

In serial communication,in order to make the system maintain flexible programmability and transplantability,minish its volume and reduce its cost,one overall architecture of clock sampling frame generator is described.Making use of FPGA characteristics and VHDL,description and definition of every module＇s IP core interface in detail has not only introduced,but also simulated and validated the IP core at the platform of ModelSim SE.At last,the design of clock sampling frame generator based on FPGA is successfully accomplished.Having been applied in practical project,the result indicates that the IP core is reliable,powerfully extensible.It has satisfied technical target of real system.