数字电路并发差错检测的新概念

NEW CONCEPTS OF CONCURRENT ERROR DETECTION FOR DIGITAL CIRCUITS

并发差错检测是提高数字电路与系统可信性的重要技术．文中建立了一种基本并发差错检测电路的结构模型，它由实现电路基本功能的基本功能模块和实现电路并发差错检测功能的检测器两部分级联所构成；提出了表征基于部分自校验概念的并发差错检测机制的一组新概念：精简强故障保险、精简强变量分离、精简强自校验、ｋ容错精简强故障保险、ｋ容错精简强变量分离和ｋ容错精简强自校验，并研究了数字电路并发差错检测的主要概念之间的关系；证明了用基本功能模块与检测器互连。

Concurrent error detection is important for improving dependability of digital circuits and systems. In this paper, a structure module for basic concurrent error detection circuit is built. It is constructed by a basic functional module and a detector. Several new concepts, reduced strongly fault secure, reduced strongly variable disjoint, reduced strongly self checking, k fault tolerant reduced strongly fault secure, k fault tolerant reduced strongly variable disjoint, and k fault tolerant reduced strongly self checking are defined to characterize circuits with partially self checking capability. The relations among all of these concepts about concurrent error detection are presented. Interconnection conditions, with which the basic functional modules and detectors must satisfy to construct basic circuits with different concurrent error detection properties, are proved.