一种支持H.264与AVS的高效环路滤波器设计

Design of Efficient In-loop De-blocking Filter Supporting H.264 and AVS

提出一种高效的多模环路滤波器,支持H.264BP/MP/HP和AVS的视频解码。为实现H.264和AVS滤波结构的复用,对宏块中需要滤波的边界作了修正;使用新颖的混合滤波顺序和宏块分割策略,提高数据的重用率,减小片上缓存;采用并行流水处理等技术提高数据吞吐量。使用65nm的CMOS工艺库,在200MHz的工作频率下综合,电路规模为43k门左右,内部存储器大小为1152byte。处理1个宏块平均需要170个时钟周期,能够支持2路H.264或AVS的1080p@60f/s高清视频解码的实时滤波处理。

An efficient in-loop de-blocking filter is proposed, which supports H.264 BP/MP/HP and AVS video decoding. In order to use the same filter architecture to process all of the H.264 and AVS MBs, the edges are redefined in a MB needed to filter. By using a novel hybrid filter order and MB division strategy, it can increase the intermediate data reuse and decreases the memory resource on chip. With pipeline and parallel process strategy, it can increase the data throughput. Adopting TSMC 65 nm CMOS technology, the proposed design is implemented with the cost of 43 k gates and 1 152 byte of local memory when operating at 200 MHz. The proposed design achieves the data throughput rate of 170 cycles per block, which meets the real-time processing requirement for two channels of H.264 or AVS 1 080p@60 f/s video coding.