基于FPGA的32位RISC微处理器设计

Design of 32-Bit RISC Microprocessor Based on FPGA

提出了一种与MIPS32指令集兼容的32位RISC微处理器(HP-MIPS)的设计方法。在对经典的MIPS体系结构分析之后,对处理器的整体结构进行重新划分,通过增加流水线级数设计出一种拥有8级流水线的微处理器数据路径结构,并且对设计中由于增加流水线级数而引入的流水线数据冲突问题给出了完整的解决方案。此外还设计了一种流水线结构的动态分支预测器用以解决微处理器分支冒险问题,其优点在于既能降低微处理器的CPI,同时又不会使流水线出现局部逻辑拥堵从而降低微处理器的主频。最后给出了设计的综合结果,并对该设计进行了软件仿真和硬件验证。在FPGA芯片上的运行时钟频率可达146.628 MHz。

A 32-bit RISC microprocessor HP-MIPS which is compatible with the MIPS32 product,is presented in the paper.After the structural analysis of the classic MIPS,the structure of the processor is re-divided.By increasing the pipeline stages a microprocessor data path structure with 8-stage pipeline is designed and an excellent solution for pipeline data hazards is provided.In addition,a pipelines dynamic branch predictor is designed for resolving branch hazards,which not only reduces the CPI of the microprocessor but also prevents the pipeline logic jams to reduce the clock speed of microprocessors.Finally,software emulation and hardware verification are implemented,and it comes out that HP-MIPS is able to run up at 146.62 MHz on FPGA chip.