基于FPGA的卷积码的编/译码器实现

Encoder and Decoder Design for Convolutional Code based on FPGA

首先阐述了(2,1,2)卷积码的原理和维特比(Viterbi)译码的实现过程,并对编码器、Viterbi译码器进行了现场可编程门阵列(FPGA)设计和实现。仿真表明了设计模块的正确性,而且能够满足速度和精度的要求。其次对最大自由距离的非恶性卷积码在高斯白噪声(AWGN)信道下的误码率性能进行分析,通过Matlab仿真表明卷积码具有很强的纠错能力,当卷积码的约束长度增大时,其误码率逐渐降低。结果表明所设计的卷积码译码器输出时延小,占用资源较少。具有一定的实用价值。

Firstly,the theory of（2,1,2） convolutional code and the process of Viterbi decoding are described.In addition,FPGA（Field Programmable Gate Array） is employed to implement encoder and Viterbi decoder.Simulation results prove the correctness of the designed modules,and these modules can meet the requirements of speed and accuraccy.Then BER（Bit Error Rate） of the maximum free distance nonmalignant convolutional code in AWGN channel is analyzed.Simulation with Matlab indicates that the convolutional code is powerful in correcting errors,and BER is increasingly reduced when the constraint length of the convolutional code become large,that the convolutional decoder is small in designed output delay,occupies fewer resources,and is of certain practical value.