期刊文献+

一种多核系统中的二维块数据存储机制 被引量:1

2D Block Data Access Mechanism in Multi-core System
下载PDF
导出
摘要 针对多核系统中处理二维数据时的数据对齐、地址映射等问题,提出一种多核系统中的二维块数据存储机制。介绍二维块数据在计算前后的数据分配、寻址及传输机制及一般应用方法,并对典型应用进行仿真验证。结果证明,该存储机制能减轻处理单元和存储单元间的不平衡性,改善一维和二维之间的不匹配现象。 To solves some common problems in 2D data processing such as data alignment and address mapping,this paper presents the mechanism of 2D block data access in multi-core system.It introduces the principle of data mapping,addressing,and data transmission.It applies a general method.Simulation result proves that the mechanism can increase the efficiency of data access and decrease the imbalance between 1D and 2D.
出处 《计算机工程》 CAS CSCD 北大核心 2011年第10期252-254,共3页 Computer Engineering
基金 国家"863"计划基金资助重点项目"嵌入式可重构移动媒体处理核心技术"(2009AA011705)
关键词 二维数据 寻址 数据对齐 地址映射 多核 2D data addressing data alignment address mapping multi-core
  • 相关文献

参考文献5

  • 1黄安文,高军,张民选.多核处理器片上存储系统研究[J].计算机工程,2010,36(4):4-6. 被引量:5
  • 2Sihvo T.A Low Cost Solution for 2D Memory Access[C] //Pros.of the 49th IEEE International Midwest Symposium on Circuits and Systems.San Juan,Puerto Rico,USA:IEEE Press,2006:123-127.
  • 3Wentzlaff D,Griffin P On-chip Interconnection Architecture of the Tile Processor[J].IEEE Micro;2007,27(5):15-31.
  • 4何军,王飙.多核处理器的结构设计研究[J].计算机工程,2007,33(16):208-210. 被引量:24
  • 5Kuzmanov G,Gaydadjiev G,Vassihadis S.Multimedia Rectangularly Addressable Memory[J].IEEE Trans.on Multimedia,2006,8(2):315-322.

二级参考文献15

  • 1Hammond L. The Standford Hydra[J]. IEEE Micro, 2000, 20(2): 71-84.
  • 2Sun Microsystems, Inc.. OpenSPARC T2 Core Microarchitecture Specification[Z]. 2007.
  • 3Nguyen T P Q, Zakhor A, Yelick K. Performance Analysis of an H.263 Video Encoder for VIRAM[C]//Proc. of IEEE International Conference on Image Processing. [S. l.]: IEEE Press, 2000: 98-101.
  • 4Seiler L, Carinean D, Sprangle E, et al. Larrabee: A Many-core x86 Architecture for Visual Computing[J]. ACM Transactions on Graphics, 2008, 27(3): 18-26.
  • 5Muralimanohar N, Balasubramonian R, Jouppi NE Architecting Efficient Interconnects for Large Caches with CACTI 6.0[J]. IEEE Micro, 2008, 28(1): 69-79.
  • 6Martin M M K, Sorin D J, Beckmann B M, et al. Multifacet's General Execution-driven Multiprocessor Simulator(GEMS) Toolset[J]. ACM SEGARCH Computer Architecture News, 2005, 33(4): 92-99.
  • 7何军,王飙.多核处理器的结构设计研究[J].计算机工程,2007,33(16):208-210. 被引量:24
  • 8Kunle O K,Basem A N,Hammond L,et al.The Case for a Single-chip Multiprocessor[C]//Proc.of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems,New York.1996-10-02.
  • 9Tullsen D M,Eggers S J,Levy H M.Simultaneous Multithreading:Maximizing On-chip Parallelism[C]//Proc.of the 22nd Ann.Int'l Symp.on Computer Architecture.1995:392-403.
  • 10Kahle J A.Introduction to the Cell Multiprocessor[J].IBM Journal Res.& Dev.,2005,49(4/5):589-604.

共引文献27

同被引文献14

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部