摘要
介绍了一种改进型超高速多体并行存储单元实现方案，采用本方案只需使用简单的外围电路的１５ｎｓ的主流存储器即可使数据吞吐率超过１００ＭＨｚ。本方案具有性能价格比高，工程实现容易，工作稳定可靠等特点。
This paper describesa realizing scheme for a modified ultra-high-rata multi-body paral1el memory unit. Adopting this scheme, the data-through-rate can exceed 100MHz. with simple periphery circuit and 15ns access times memory. The scheme has the advantage of high price performance ratio, project-achieving easy. working steady and credible ect.
出处
《指挥技术学院学报》
1999年第2期76-80,共5页
Journal of Institute of Command and Technology
