片上一体化霍尔传感器的优化设计

Optimization of integrated hall sensor

设计了1款片上一体化霍尔传感器芯片。现有的霍尔传感器使用的采样保持电路需要用到较大电容,在芯片占用面积较大,并且传感器的灵敏度受供电电压波动影响较大,不利于芯片稳定工作。设计通过对原有锁存型霍尔传感器结构进行调整,用反馈式磁滞比较器取代的采样保持电路与施密特触发电路,来完成磁滞比较功能,在有效消除霍尔盘和运放失调电压的前提下,节省芯片面积,稳定芯片灵敏度,提高了芯片的稳定性。设计用华润上华数模混合0.5μCMOS工艺设计仿真验证,仿真结果与理论结果相吻合,完成版图设计并已MPW。

Presents a new structure of integrated hall sensor.Normal Hall sensor has a higher area cost in chip as large capacitance is used in the sample hold block contained in the circuit.And the sensitivity of the sensor is affected by the supply voltage,as makes the Hall chip unstable.In this design,a feedback comparator is used to take the place of sample hold block and Schmitt trigger block.By using the new structure,the sensitive voltage has no relationship with the voltage supply,as has enhanced the stability of the sensor and decreased the area cost of the chip.The design has been simulated and checked by CSMC 0.5μ CMOS technology.The layout has been finished and the design has been taped out.