数字调节器采样周期的设计

The Design of Digital Regulator Sampling Period

数字调节器的设计，无论是从系统闭环脉冲传递函数或从采样定理去求取采样周期都不容易。以满足动态性能要求为依据，概括归纳出两种采样周期的工程设计方法，使用简便，既能满足动态性能要求，又不违背采样定理。

It's at easy for digital regulator to get sampling period either ho system closed -loop pulsetransfer function or from sampling theorem.Two engineering designs on sampling period are sununarrized.They're easy to use and can sitysfy the dynamic requirement and are not violation sampling theorem.