低阻硅CMOS工艺片上互连线模型

Model of On-chip Interconnect Line in Low-resistance Si CMOS Substrate

提出了一种新的互补金属氧化物半导体(CMOS)工艺片上的互连线模型,模型在考虑互连线金属导体高频效应和衬底效应的基础上,引入了一个电容来表征金属导体通过氧化层在低阻硅衬底中引起的容性耦合特性。建立的互连线模型通过0.18μm CMOS工艺上制作的互连线测试数据验证,频率精度可至50 GHz。

A new model of on-chip interconnection line in CMOS substrate has been proposed in this paper.A capacitor was introduced to characterize the capacitive coupling caused by the metal conductor through the oxide layer in the low-resistance Si substrate by considering the high frequency characteristics of metal conductor and the substrate effect in the model.The model parameters can be extracted from the layout and process parameters and the measured data.The validity of the proposed model has been verified up to 50 GHz with sample interconnect line fabricated in 0.18 μm RF CMOS technology.