摘要
本文阐明了逻辑电路易测性设计的目的及其电路应具备的特点;介绍了五种简化测试的具体方法;推导出了使组合电路具有良好易测性的一种特殊结构形式,即里德—马勤(Rced—Muller)扩展式,并进行了实例分析。
The targets of the ready TESTABILITY design for logic circuits and their necessary attributes are introduced,together with 5 specific,simplified testing methods;and a special constructive formulation for making the combinational circuits readily testable is derived-the expanded Reed-Muller Circuit-including some case studies.
关键词
易测性设计
逻辑电路
ready testability design
test pattern
test point
module
expanded Reed-Muller circuit
