高性能可编程互连资源设计研究

High Performance Programmable Interconnect Resource Design Investigation

传统的可编程互联结构在短距离互连上往往采用单管、中距离上有双向线,这使得在CLB中查找表(LUT)数目变大后,互连上的延迟会随线长增加而呈指数增长.本文提出了一种改进的高性能互连结构,改进了短、中和长距离互连,使得其在CLB中LUT数目增加的情况下让芯片拥有更好的互连延迟特性,通过对这种互连结构和传统的互连结构进行建模仿真并对延迟性能比较,结果显示,两倍线的平均延迟降低了21.9%、六倍线的平均延迟均降低了近21.7%,长线平均延迟降低了约4%.这种高性能互连结构应用于我们自主研发设计的FDP2009-2-SOPC芯片中,并对其互连性能进行了测试,验证了我们的思想.

Conventional FPGAs use transistor switch in short range interconnection and bidirectional mid range lines,which would make the interconnection delay grows exponentially with the wire length as the number of Look Up Table（LUT） in CLB increases.In this article,we present an improved high performance routing architecture,whose short,mid and long range lines are improved to make the interconnect resource has a better delay performance when the CLB tends to become larger and contains more programmable logic resource and the area of CLB grows larger,and compare its performance with the conventional FPGA＇s routing architecture by modeling and simulation.Through the comparison,we know that using this new architecture,the double lines are average 21.9% faster,the hex lines are average 21.7% faster,and the lone lines are average 4% faster.And this routing architecture has already been used in the FDP2009-2-SOPC FPGA chip,which is designed and taped out by ourselves.And we also have finished the performance test of its routing resources and proved the superiority of our idea.