期刊文献+

一种连续/离散混合结构的电容数字自校准Sigma Delta模数转换器设计 被引量:1

A Mixed CT/DT ΣΔ ADC with Capacitor Digital Self-Calibration for RC Spread Compensation
下载PDF
导出
摘要 本文根据连续时间调制器和离散时间调制器的各自优缺点,提出了一种新型混合调制器结构的音频Sigma Delta模数转换器,电容数字自校准电路用来补偿连续时间积分器的RC常数,斩波稳定技术用来降低深亚微米CMOS工艺下的闪烁噪声.测试结果表明连续/离散混合结构Sigma Delta模数转换器的峰值信噪比达到102dB,芯片总体功耗为30mW. This paper provides a mixed continuous-time/discrete-time sigma delta ADC.This ADC combines the benefits of CT and DT circuits,and the self-calibration control circuits compensate for the variation of the RC product in the continuous-time integrator.Chopper stabilization can remove the flicker noise especially problematic in deep submicron MOS devices.Measurement results show that the peak SNR of this ADC reaches 102dB and the total power consumption is less than 30mW.
出处 《电子学报》 EI CAS CSCD 北大核心 2011年第5期1185-1189,共5页 Acta Electronica Sinica
关键词 连续时间 离散时间 斩波稳定 自校准 SigmaDelta模数转换器 continuous-time discrete-time chopper stabilization self-calibration sigma delta ADC
  • 相关文献

参考文献6

  • 1Ammisetti Prasad, Amiya Chokhawala. A 120dB 300mW stereo audio A/D converter with 110dB THD + N [J].IEEE Journal of Solid-State Circuits, 2004,39(14) : 191 - 194.
  • 2YuQing Yang,Amiya Chokhawala. A 114-dB 68-mW chopper- stabilized stereo multi-bit audio ADC in 5.62mm2 [J]. IEEE Journal of Solid-State Circuits,2003,38(12) :2061- 2068.
  • 3P Morrow, et al. A 0.18um 102dB-SNR mixed CT SC audioband ADC [J].IEICE Tech Rep,2005, 105(96) :35 - 38.
  • 4Jian Yi Wu, Rajaram. A 107.4dB SNR multi-bit siena delta ADC with 1-PPM THD at -0.12dB from full scale input [J].IEEE Journal of Solid-State Circuits, 2009,44(11) :3060 - 3066.
  • 5王慧,刘正士,汪家慰,王勇.测试高分辨率ADC有效位数的HHT方法[J].电子学报,2009,37(9):2072-2076. 被引量:9
  • 6于慧敏,刘圆圆,王哲.信号的低比特位数表示:一种新颖低比特位数的Σ-Δ调制器[J].电子学报,2004,32(6):983-986. 被引量:1

二级参考文献14

  • 1龚志强,邹明玮,高新全,董文杰.基于非线性时间序列分析经验模态分解和小波分解异同性的研究[J].物理学报,2005,54(8):3947-3957. 被引量:78
  • 2JJF1053-1998,数字存储示波器校准规范[S].
  • 3IEEE Std 1057- 1994,IEEE Standard for Digitizing Waveform Recorders, Waveform Measurements and Analysis[ S ].
  • 4IEEE Std 1057 - 1994, Standard for Digitizing Waveform Recorders[ S].
  • 5IEEF, Std 1241 - 2000, Standard for Terminology and Test Methods for Aoalogy-to-Digital Converter[ S ].
  • 6Jiang H J,Beatriz Olleta,Chen D G,et al. Testing high-resolution ADCs with low-resolution/accuracy deterministic dynamic element matched DACs[ J]. IF.EF. Trans Instrum Meas, 2007, 56(5) : 1753 - 1762.
  • 7Huang N E,Shen Z,Long S R,et al.The empirical mode decomposition and the Hilbert spectrum for non-linear and nonstationary time series analysis[ J] .Proceedings of the Royal Society, 1998,454(1971) :903 - 995.
  • 8H Inose. Y Yasuda. A unity bit coding method by negative feedback[J].Proc IEEE, 1963,51:1524-1535.
  • 9Orla Feely, Leon O C hua. The effect of integrator leak in Σ-A modulation[J]. IEEE Transaction on Circuits and Systems, 1991,38 (11):
  • 10Rex T Baird, Terri S Fiez. Stability analysis of high-order delta-sigma modulation for ADC's[J]. WEE Transitions on Circuits and systemsⅡ:Analog and digital signal processing, 1994,41 (1):

共引文献8

同被引文献10

  • 1KAPPES M S. A 2. 2-mW CMOS bandpass continuous- time multibit ∑△ A1-K; with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications [J]. IEEE J Sol Sta Circ, 2003, 38(7): 1098-1104.
  • 2PATON S, GIANDOMENICO A, HERNANDEZ L, et al. A 70-mW 300-MHz CMOS continuous-time sigma-delta ADC with 15-MHz bandwidth and 11 bits of resolution [J]. IEEE J Sol Sta Circ, 2004, 39(7) : 1056-1063.
  • 3PAVAN S. Excess loop delay compensation in continuous- time delta-sigma nxxtulators [J]. IEEE Trans Circ & Syst Ⅱ, 2008, 55(11): 1119-1123.
  • 4WANG Wenting, LOU Shuzuo, CHUI K, et al. A single-chip UHF RFID reader in 0. 18 μm CMOS process [J]. IEEE J Sol Sta Circ, 2008, 43 (8): 1741-1754.
  • 5SCHREIER R, TEMES G C. Understanding delta- sigma data converters [M]. New York: IEEE Press, 2005.
  • 6MALCOVATI P, BRIGATI S, FRANCESCONI F, et al. Behavioral modeling of switched-capacitor sigma-delta modulators [J]. IEEE Trans Circ &Syst I, 2003, 50(3): 352-364.
  • 7ORTMANNS M, GERFERS F, MANOLI Y. A case study on a 2-1-1 cascaded continuous-time sigma-delta modulator [J]. IEEE Trans Cire & Syst I, 2005, 52 (8) : 1515-1525.
  • 8GERFERS F, ORTMANNS M, MANOLI Y. A 1.5-V 12-bit power-efficient continuous-time third- order ∑△ modulator [J]. IEEE J Sol Sta Circ, 2003, 38(8) : 1343-1352.
  • 9苏小波,柴旭朝,戴欢,顾晓峰,于宗光.用于MEMS传感器的三阶Σ-Δ调制器设计[J].微电子学,2010,40(5):701-704. 被引量:4
  • 10冯筱,文光俊,陈健,王耀,刘佳欣.适于UHF RFID标签芯片的高性能电源恢复电路[J].微电子学,2012,42(2):159-163. 被引量:1

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部