基于安全控制边界单元的IP核测试封装方法

Secure Test Wrapper Design for Embedded IP Cores

为了解决测试信息传递的问题,IEEE组织推出了IEEE1500 IP(Intellectual Property)核测试封装标准以标准化IP核测试接口.然而该标准给出的典型测试封装存在由测试数据扫描移入造成的不安全隐患.本文提出了一种基于安全控制边界单元的IP核测试封装方法.这种方法的核心思想是在典型的测试封装边界单元的基础上添加一个CMOS(Complementary Metal Oxide Semiconductor)传输门,有效消除了测试过程中扫描移位对被测IP核电路的影响.实验结果表明,这种基于安全控制边界单元的测试封装能够在完成测试任务的同时,有效降低IP核输入端口的测试数据数据跳变次数,使IP核处于安全状态,还可以降低扫描移位过程中产生的动态测试功耗.

The IEEE 1500 standard was proposed to standardize the IP（Intellectual Property） core test interface to transfer test information.But the typical IEEE 1500-compliant test wrapper would lead IP cores into an insecure status during scan shifting.This paper presented a secure test wrapper design for embedded IP cores,which only inserted a CMOS（Complementary Metal Oxide Semiconductor） transmission gate to the test wrapper cell to eliminate the precarious effect to IP cores.Experiments show that the proposed test wrapper not only takes less area overhead and time delay,but also can test the data path and reduce the data transitions at the input port of IP cores,thus decreases the dynamic test power during scan shifting.