A 20 μW 95 dB dynamic range 4th-order Delta-Sigma modulator with novel power efficient operational transconductance amplifier and resonator

A low power high performance Delta-Sigma modulator for portable measurement applications is presented. To reduce power consumption while maintaining high performance, a fully feedforward architecture with a comprehensive system-level design is implemented. As a key building block, a novel power efficient current mirror operational transconductance amplifier (OTA) with a fast-settling less-error switched-capacitor common-mode feedback (SC CMFB) circuit is introduced, and the effects of both gain nonlinearity and 1/f noise of OTA are discussed. A new method to determine the voltage gain of an OTA is also proposed. The bottom terminal parasitic effect of poly-insulator-poly (PIP) capacitors is considered. About an extra 20% of capacitance is added to the total capacitance load. A power and area efficient resonator is adopted to realize a coefficient of 1/90 for 50% power and 75% area reduction compared with conventional designs. The chip is implemented in a low cost 0.35 μm complementary metal oxide semiconductor (CMOS) process. The total power consumption is 20 μW with a 1.5 V supply, and the measured dynamic range (DR) is 95 dB over a 1 kHz bandwidth. Experimental results show that a high figure-of-merit (FOM) is achieved for the designed modulator in comparison with those from the literature.

A low power high performance Delta-Sigma modulator for portable measurement applications is presented. To reduce power consumption while maintaining high performance, a fully feedforward architecture with a comprehensive system-level design is implemented. As a key building block, a novel power efficient current mirror operational transconductance amplifier （OTA） with a fast-settling less-error switched-capacitor common-mode feedback （SC CMFB） circuit is introduced, and the effects of both gain nonlinearity and l/f noise of OTA are discussed. A new method to determine the voltage gain of an OTA is also proposed. The bottom terminal parasitic effect of poly-insulator-poly （PIP） capacitors is considered. About an extra 20% of ca- pacitance is added to the total capacitance load. A power and area efficient resonator is adopted to realize a coefficient of 1/90 for 50% power and 75% area reduction compared with conventional designs. The chip is implemented in a low cost 0.35 pan com- plementary metal oxide semiconductor （CMOS） process. The total power consumption is 20/xW with a 1.5 V supply, and the measured dynamic range （DR） is 95 dB over a 1 kHz bandwidth. Experimental results show that a high figure-of-merit （FOM） is achieved for the designed modulator in comparison with those from the literature.