期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

An efficient hardware design for HDTV H.264/AVC encoder

An efficient hardware design for HDTV H.264/AVC encoder
原文传递
导出
摘要 This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile. This paper presents a hardware efficient high definition television （HDTV） encoder for H.264/AVC. We use a two-level mode decision （MD） mechanism to reduce the complexity and maintain the performance, and design a sharable archi- tecture for normal mode fractional motion estimation （NFME）, special mode fractional motion estimation （SFME）, and luma motion compensation （LMC）, to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio （BD-PSNR） decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.
作者 Liang WEI
机构地区 Institute of Information and Communication Engineering Zhejiang Provincial Key Laboratory of Information Network Technology
出处 《Journal of Zhejiang University-Science C(Computers and Electronics)》 SCIE EI 2011年第6期499-506,共8页 浙江大学学报C辑（计算机与电子（英文版）
基金 supported by the National Natural Science Foundation of China (No. 61076021) the Program for New Century Excellent Talents in Universities, China
关键词 H.264/AVC High-definition television (HDTV) HARDWARE ARCHITECTURE ENCODER H.264/AVC, High-definition television （HDTV）, Hardware, Architecture, Encoder
分类号 TN919.8 [电子电信—通信与信息系统]
  • 相关文献

参考文献12

  • 1Chang, T.C., Chen, J.W., Su, C.L., Yang, Y.C., Li, Y., Chang, C.H., Cben, Z.M., Yang, W.S., Lin, C.C., Chen, C.W., et al., 2007. A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. IEEE Int. Solid-State Circuits Conf., p.280-281. [doi:10.1109/ISSCC.2007.373 403].
  • 2Chen, T.C., Chien, S.Y., Huang, Y.W., Tsai, C.H., Chen, C.Y., Chen, T.W., Chen, L.G., 2006. Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. IEEE Trans. Circ. Syst. Video Technol., 16(6):673- 688. [doi: 10.1109/TCSVT.2006.873163].
  • 3Chen, Y.H., Chuang, T.D., Chen, Y.J., Li, C.T., Hsu, C.J., Chien, S.Y., Chen, L.G., 2008. An H.264/AVC Scalable Extension and High Profile HDTV 1080p Encoder Chip. IEEE Symp. on VLSI Circuits, p. 104-105. [doi: 10.1109/ VLSIC.2008.4585969].
  • 4Huang, Y.W., Chert, T.C., Tsai, C.H., Chen, C.Y., Chen, T.W., Chen, C.S., Shen, C.F., Ma, S.Y., Wang, T.C., Hsieh, B.Y., et al., 2005. A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV Applications. IEEE Int. Solid-State Circuits Conf., p.128-133. [doi:10.1109/ISSCC.2005.149 3902].
  • 5ITU-T, 2005. ITU-T Recommendation and International Standard of Joint Video Specification. H.264/ISO/IEC 14496-10 AVC.
  • 6Lee, K.H., Alshina, E., Park, J.H., Han, W.J., Min, J.H., 2008. Technical Considerations for Ad Hoe Group on New Challenges in Video Coding Standardization. MPEG Doe. M15580. Hannover, Germany.
  • 7Lin, Y.K., Lin, C.C., Kuo, T.Y., Chang, T.S., 2008a. A hardware-efficient H.264/AVC motion-estimation design for high-definition video. 1EEE Trans. Circ. Syst. 1, 55(6): 1526-1535. [doi:10.1109/TCS1.2008.916681].
  • 8Lin, Y.K., Li, D.W., Lin, C.C., Kuo, T.Y., Wu, S.J., Tai, W.C., Chang, W.C., Chang, T.S., 2008b. A 242mW, 10mm^2 1080p H.264/AVC High Profile Eneoder Chip. 45th ACM/IEEE Design Automation Conf., p.78-83.
  • 9Liu, Z.Y., Song, Y., Shao, M., Li, S., Li, L.Y., Ishiwata, S., Nakagawa, M., Goto, S., Ikenaga, T., 2009. HDTV1080p H.264/AVC encoder chip design and performance analysis. IEEE J. SoL-State Circ., 44(2):594-608. [doi:10. 1109/J88C.2008.2010797].
  • 10Park, S.H., Lee, J.H., 2008. Hardware Architecture for Real-Time HD(1920x1080@60fps) H.264/AVC Intra Prediction. IEEE Int. Symp. on Consumer Electronics, p.1. [doi:]0.1109/19CE.2008.4559505].
Journal of Zhejiang University-Science C(Computers and Electronics)
2011年 第6期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部