摘要
本文在W.Li(1991)循环斜卷积算法和分布式算法的基础上,通过软件模拟和具体硬件设计,利用FPGA完成了可用于高清晰度电视核心解码器及其它信号与信息处理系统的8×8二维DCT/IDCT处理器的全部电路设计工作。它采用一根信号线控制计算DCT/IDCT,其输入、输出为12位,内部数据线及内部参数均为16位。
Based on the skew-circular convolution distributed algorithm presented by W.Li(1991). A 8×8 2-D DCT/IDCT processor has been designed using FPGAs, which can be used for HDTV's decoder or other signal and information processing systems. It can be used to calculate either DCT or IDCT depending on a single control line. AM of the input/output are 12-bit and the internal data bus and internal parameters are 16-bit.
关键词
二维DCT/IDCT
处理器
分布式算法
FPGA(Field Programmable Gate Arry), 2-D DCT/IDCT processor, Distributed algorithm
