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一种嵌入式FPU的设计与实现 被引量:3

A Design of Special Purpose FPU
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摘要 本文介绍了自主设计实现的浮点部件NRSFPU(Northwestern Polytechnical University RISCSystem′sFloating Point Unit).为了优化设计规模和速度,在体系结构设计中采用了有效策略,并给出了NRSFPU 中复杂运算指令流程的设计.通过布局布线后的结果看出,该设计规模小,速度高。 To meet the needs of embedded application,this paper describes NRS FPU(Northwestern Polytechnical University RISC System′s Floating Point Unit)thoroughly.Our discussions in this paper centre on NRS FPU system architecture,basic arithmetic operation and transcendental function operation algorithms.NRS FPU is designed by a very popular way —— TOP DOWN and with RISC idea.Since add and shift are two basic operations in arithmetic circuits,many algorithms based on them are conceived to implement complex arithmetic functions in this paper.Finally,it is shown that NRS FPU is much suitable for embedded application due to its small area and high speed from its layout.
出处 《电子学报》 EI CAS CSCD 北大核心 1999年第10期119-121,共3页 Acta Electronica Sinica
关键词 浮点部件 FPU NRSFPU 浮点执行部件 FXU floating point unit(FPU) NRS FPU floating point execution unit(FXU)
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  • 1詹文法,汪国林,杨羽,张珍.32位快速乘法器的设计[J].合肥工业大学学报(自然科学版),2004,27(9):1099-1102. 被引量:2
  • 2王颖,林正浩.快速浮点加法器的优化设计[J].电子工程师,2004,30(11):24-26. 被引量:4
  • 3RLHummel著 朱莉 张龙译.80X86处理器和80X87协处理器大全[M].电子工业出版社,1994.3.
  • 4[3]Charles Farnum.Compiler Support for Floating-Point Computation[J].Software Practices and Experience,1988,7 (18):9 -21.
  • 5[6]A.Kunimatsu et.Al.Vector Unit Architecture for Emotion Synthesis[J].IEEE Micro,2000,20(2):40-47.
  • 6Raymond Heald, Kathirgamar Aingaran. A Third-Generation Sparc V9 64-b Microprocessor. IEEE Journal of Solid-State Circuits. November, 2000, 35(11).
  • 7Raft Nave. Implementation of Transcendental Functions on a Numerics Processor. North Holland,Microprocessing and Microprogramming, 1983.11.
  • 8于敦山,沈绪榜.32位定/浮点乘法器设计[J].Journal of Semiconductors,2001,22(1):91-95. 被引量:22

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