用于片上网络的准延时不敏感全异步仲裁器

Quasi delay-insensitive full asynchronous arbiter for the network on chips

针对传统片上网络不同方向请求信号之间的优先级动态变化带来的服务质量问题,设计了一种延时不敏感全异步仲裁器.这种仲裁器具有自检测优先级功能,可以通过动态检测输入请求的优先级变化来自动选择两种输出方式(优先输出方式和顺序输出方式),解决了传统片上网络中的静态仲裁机制带来的端口服务固定化问题.通过将输入请求锁存使仲裁模块和输出模块解耦合,大大提高了仲裁的稳定性.使用门限门使整个仲裁器准延时不敏感.最后,在0.18μm标准CMOS工艺下实现了此仲裁器,结果表明,此全异步仲裁器平均仲裁时间为1.175 ns,平均动态功耗为1.53mW,可以满足高速片上网络的仲裁要求.

This paper proposes a quasi delay-insensitive full asynchronous arbiter for the network on chips. With the function of priority self-detection, it improves the quality of service given by the priority variations of data packages from different directions. It can automatically select one of output schemes according to dynamically detecting the changes of priority in data packages, solving the problems of ports priority fixation in the conventional static arbitration mechanism. The stability of arbitration is greatly enhanced owing to decoupling the arbitration module from the output module by locking input requests. The application of the threshold gate makes the whole arbiter quasi delay-insensitive. The arbiter is implemented in 0. 18 ~m standard CMOS technology. Results have shown that the average arbitration time is 1. 175 ns with average dynamic power consumption of 1.53 mW, which can fulfill the demand of high-speed on-chip data package arbitration.