考虑非均匀温度分布的RLC互连延时

RLC interconnect delay with nonuniform temperature distribution

为解决高性能集成电路设计中互连延时估算精确较低的问题,在分析互连温度分布的基础上,提出一种考虑非均匀温度分布效应的互连延时模型,该模型基于电感转化为等效电阻的思想,将互连电感效应整合到所提模型中.针对65 nm工艺,讨论3种典型的非均匀温度分布以及电感效应对互连延时的具体影响,以电路模拟程序Hspice为参照,将所提模型与同类模型进行比较,仿真结果显示本文模型更为精确,最大误差不超过3.3%.同时本文模型具有闭合的解析形式,公式简洁,可有效地提高计算效率.

In order to improve the bad accuracy of interconnect delay estimation, a new interconnect delay model considering the nonuniform temperature distribution was presented on the basis of the analysis of temperature distribution along interconnect in this paper. The proposed model incorporated interconnect inductance effect based on the thought of considering inductance as equivalent resistance. For 65 nm process technology, the paper discussed the impacts of three kind of nonunifor temperature distribution and inductance effect on interconnect delay. Results show that our proposed model with less than 3.3 % error is more accurate than the other available similar models by comparing the results of Hspice. At the same time, the proposed analytical model with simple expression has closed-form expression and improves the calculation efficiency.