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高速高精度模/数转换的微机动态轨道衡 被引量:3

A MICROCOMPUTERIZER DYNAMIC RAILWAY SCALE WITH HIGH SPEED AND HIGH GLASS ACCURACY A/D CONVERSION
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摘要 介绍了微机动态轨道衡的工作原理,探讨了动态称重特点和软件数据处理方法,提出了采用高速A/D 转换器及数字滤波来消除振动干扰误差的方法.现场测试数据分析表明,动态称重技术指标达到了国家动态检衡标准. Simple working principle of microcomputerized dynamic railway scale is presented in this paper, its specific property and the date processing method for dynamic weighing are discussed. High speed A/D converter and digital filter are used in order to reduce the error of vibration disturb. Analysis of the testing data indicates that its technical criterion comes up to the national standard of dynamic weighting.
作者 凌玉华
出处 《中南工业大学学报》 CSCD 北大核心 1999年第6期623-625,共3页 Journal of Central South University of Technology(Natural Science)
关键词 动态轨道衡 模/数转换 数据处理 精度 微机 dynamic railway scale A/D converter data processing precision
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  • 1Veendrick H J M. The behavior of flip-flops used as synchronizers and prediction of their failure Rate[J]. IEEE J Solid-State Circuits, 1980, 15(2): 169-176.
  • 2Boni A, Chiorboli G, Morandi C. Dynamic characterisation of high-speed latching comparators[J]. IEEElectron Lett, 2000, 36(5): 402-404.
  • 3Sumanen L, Waltari M, Hakkarainen V, et al. CMOS dynamic comparators for pipeline A/D converters[J]. IEEE Int Symp on Circuit and Systems, 2002, 5: 157-160.
  • 4Goll B, Zimmermann H. A low-power 2-Gsample/s comparator in 120 nm CMOS technology[C]// Proceedings of ESSCIRC. Grenoble, France, 2005:50?-511.
  • 5Uyttenhove K, Steyaert M S J. A 1.8 V 6-Bit 1.3 GHz flash ADC in 0.25 m CMOS[J]. IEEE J Solid-State Circuits, 2003, 38(7): 1115-1122.
  • 6Wong K L J, Yang C K K. Offset compensation in comparators with minimum input-referred supply noise[J]. IEEE J Solid-State Circuits, 2004, 39(5): 837-840.
  • 7Abidi C. A 6b 1.3Gsample/s A/D converter in 0.35 μm CMOS[J]. IEEE J Solid-State Circuits, 2001, 36: 1847-1858.
  • 8Dalton M. A 500-MSample/s, 6-b nyquist-rate ADC for disk drive read-channel application[J]. IEEE J Solid-State Circuits, 1999, 34:912-920.
  • 9Sheikhaei S, Mirabbasi S, Ivanov A. A 0.35 μm CMOS comparator circuit for high-speed ADC applications[C]//IEEE Int Syrup Circ and Syst. 2005: 6134-6137.
  • 10Abo A M, Gray P R. A 1.5-V, 10-bit,14.3-MS/s CMOS pipeline analog-to-digital converter[J]. IEEE J Solid-State circuits, 1999, 34(5): 599-606.

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