用于射频SOC芯片的低噪声高电源抑制比LDO

A Low Noise High PSRR LDO for RF SOC Applications

设计了一种能够为射频芯片提供低噪声、高PSRR、全集成LDO。采用SMIC 0.18μm RF工艺实现,芯片有效面积0.11 mm^2。测试结果表明:当输出电流从0跳变为20 mA时,最大Ripple为100 mV,稳定时间2μs;当输出电流为20mA,频率到1 MHz的情况下,PSRR<-30 dB;从1～100 kHz的频率范围内输出电压积分噪声为21.4μVrms;在整个工作电压范围内(2.1～3.3 V)输入电压调整率<0.1%;在整个输出电流的范围内(0～20 mA),负载调整率<0.44%;LDO消耗了380μA的电流(其中Bandgap消耗了260μA的电流)。

A low noise high PSRR fully integrated LDO for RF SOC applications is presented. The regulator was fabricated in SMIC 0. 18μm RF process. The active die area is 0. 11 mm^2. Experimental results show that the output voltage can recover within 2 μs with less than 100 mV ripple when a full load current changes from 0 to 20 mA. The power supply rejection ratio remains below -30 dE when frequency is up to 1 MHz for the loading current up to 20 mA. The integrated noise from 1 to 100 kHz is 21.4 μVrms. The line regulation is controlled below 0. 1%, throughout the full input voltage range from 2.1 to 3.3 V. The load regulation is controlled below 0.44% ,throughout the full load current range from 0 to 20 mA. The power consumption is 380 μA （260 ttA for bandgap）.