基于数字鉴频器的新型微波锁相环捕获方法

Capture Method for Novel Microwave PLL With Digital Frequency Discriminator

为了提高锁相环锁定速度,在研究快速捕获技术基础上提出一种新型的数字鉴频器的设计方法,然后对一个频率范围在1-8 GHz、频率步进为10 MHz的宽带锁相频率源进行了设计与实现.该方法利用鉴频器对压控振荡器的频率进行精确预置,使其进入锁相环快捕带,实现对锁相环宽带捕获和精确预置.测试结果表明,该锁相频率源相位噪声低,杂散小;采用该方法,捕获时间有了较大的改善.

To enhance the lock speed in PLL,this paper presents a novel design scheme for the digital discriminator based on studying the fast capture techniques,then,design a wideband phase-locked frequency source with the frequency range 1 8 GHz and step 10 MHz,and finally implement the source.In the scheme,the frequency of VCO in PLL can be preset precisely by using the designed frequency discriminator,allowing the former to get into the fast capture band of the PLL,and thus fulfilling the wideband capture and precise preset of the PLL.The test results show that the proposed PLL frequency source is of lower phase,smaller spur,and the capture time is of much improvement using the proposed scheme.