面向序列密码的抽取与插入单元可重构设计研究

Research on reconfigurable extract and insert units targeted at stream cipher algorithms

研究了抽取与插入单元的基本原理,提出了一种可重构的抽取与插入硬件电路,并对核心模块控制信息生成电路进行了深入研究。可重构硬件电路通过配置能够灵活高效地实现32 bit、64 bit、128 bit、256 bit等位宽抽取与插入操作。该设计在Altera公司的FPGA上进行了功能验证,并在Synopsys公司的Design Compiler上进行了逻辑综合、优化。结果表明,在CMOS 0.13μm工艺下,可重构移位单元硬件架构核心频率可以达到350 MHz。

This paper presents a high-performance and flexible reconfigurable methodology for extract and insert units by studying the fundamental principle. The reconfigurable extract and insert units are designed to sustain variety data widths operations, such as 32 bit,64 bit,128 bit,256 bit. The design has been realized using Altera＇s FPGA and synthesized and optimized on Synopsy＇s Design Compiler .The result proves that the maximum frequency can achieve 350 MHz on 0.13 p,m CMOS technology.