基于FPGA的雷达恒虚警模块的设计

Design of a radar CFAR module based on FPGA

恒虚警处理技术可以使雷达在保持较高发现概率的同时,降低虚警概率。为了提高机载雷达在杂波与噪声背景条件下发现目标的能力,针对复杂统计模型应用的局限性,提出了一种基于FPGA的恒虚警模块的设计思想,并在软件平台环境下,对设计方法的可行性进行了仿真验证。

The processing technique of CFAR can reduce false alarm rate while maintain high detection probability. In order to enhance the ability to find objections for a-radar which is under the ground of noise and clutter, the text proposes a designation of CFAR module based on FPGA which aims at the limited application of complex statistical model , and makes simulation and testing to verify the feasibility of design method under the environment of OSVM.